This paper proposes the first efficient stuck-at and transition-delay fault test generation algorithm able to prove testability or untestability of faults in presence of X-values. In presence of X-values, conventional test generation algorithms, based on structural algorithms, Boolean satisfiability (SAT), or binary decision diagram-based reasoning may fail to generate test patterns or to prove faults untestable. To compute a test pattern for a given fault, well-defined logic values are required both for fault activation and propagation to observing outputs. X-sources are for instance black boxes in design models, clock-domain boundaries, analog-to-digital converters, or uncontrolled or uninitialized sequential elements. Unknown (X) values emerge during the design process as well as during system operation and test application. ![]() Our experimental results show that depending on the incorporated D-chain the runtime can be reduced tremendously. In addition, we propose a new indirect D-chain algorithm with two extensions. In this paper we present a thorough investigation of the different D-chain concepts to evaluate which is the best method for different problems. However, none of the previous publications tried to analyze and evaluate which of these methods is the most beneficial. With the advent of incremental solving new concepts like the backward D-chain or even more recently an indirect D-chain were introduced. In return, this forces the solver to only consider assignments that might lead to a valid test pattern and thus reduce the search space. In order to increase the solving speed introduced the concept of D-chains which add additional information to the mathematical model. ![]() A specialized solver evaluates this representation to determine the testability of faults and extracts a test pattern in case a satisfying assignment was found. One of the best known methods is SAT-based automatic test pattern generation (ATPG) which, in contrast to classical structural ATPG, first generates a mathematical representation of the problem in form of a Boolean formula. With the ever increasing size of today's Very-Large-Scale-Integration (VLSI) designs new approaches for test pattern generation become more and more popular. In this work we perform a thorough analysis and evaluation of the D-chain variants for test pattern generation and also analyze the impact of different D-chain encodings on diagnostic test pattern generation. In the past, different variants of D-chains have been developed, such as the backward D-chain or the indirect D-chain. Thereby supplementary clauses are added to the Boolean formula, reducing the search space and guiding the solver toward the solution. In order to speed up test pattern generation, the concept of D-chains was introduced by several researchers. If the considered fault is testable, the solver will return a satisfying assignment, from which a test pattern can be extracted otherwise no such assignment can exist. SAT-based automatic test pattern generation (ATPG) is one of the most popular methods, where, in contrast to classical structural ATPG methods, first a mathematical representation of the problem in form of a Boolean formula is generated, which is then evaluated by a specialized solver. The ever increasing size and complexity of today’s Very-Large-Scale-Integration (VLSI) designs requires a thorough investigation of new approaches for the generation of test patterns for both test and diagnosis of faults. Experimental results, obtained on a wide range of publicly available benchmarks, demonstrate that the new model allows significant performance improvements over other well-established models. The proposed model is fundamentally different from previous SAT-based ATPG models in that the number of used variables is significantly reduced. This paper proposes a new model for SAT-based ATPG. ![]() ![]() Interestingly, despite the potential interest of more efficient ATPG approaches, the core SAT-based ATPG model has remained essentially unchanged since it was first proposed in the late 80s. Moreover, ATPG models and algorithms find application in a number of other settings, that further motivate the development of more efficient SAT-based ATPG solutions. Recent work on SAT-based ATPG has been motivated by industrial designs with ever increasing size, for which more efficient ATPG tools are essential. Even though ATPG can in general be considered easy for current state of the art SAT solvers, it is also the case that specific faults can be difficult to detect or prove undetectable, namely for large industrial circuits. Automatic Test Pattern Generation (ATPG) represents one of the first practical applications of Boolean Satisfiability (SAT).
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